Fun with playing around the TI 5121 DAC.

modes

pp 6:

i2c interface

pp 55:

Write: 0x98 - 10011000 Read: 0x99 - 10011001

i2s interface on BCM

page 119

but how do I set the master clock?

Heh. Its not documented. Go figure. Fortunately, https://firmanhp.com/assets/20241005-id-raspi-bare-metal-rust/pdf/BCM2837-ARM-Peripherals-Revised-V2-1.pdf seems to tell us what to do:

There are two PCM/I2S clock control registers.

CM_PCM_CTRL @ 0x7E101098

• Bit 5 = Emergency Stop; should be 0; debugging only
• Bit 4 = Clock Enable
• Bits 3:0 = Clock Source

OSC (SRC=0b0001) is cool and allegedly good, but it runs on 19.2 which is less than crispy crispy 48khz so we are going to use PLLD (SRC=0b0110) which runs at a cheeky 500MHz nominal.

CM_PCM_DIV @ 0x7E10109C

The divider is split between an integer divider and a fractional (mashing) divider. The mashing dividers are build such that clock artifacts should be pushed out of the audio frequency domain.

• Bits 31:24 = you have to put the value 0x5A here
• Bits 23:12 = the integer divider.
• Bits 11:0 = the mashing divider.

See page 105 in BCM2835-Peripherals for MASH math.

DWIM (Do What I Mean) for the inpatient and numerically inept

32 bits per slot and two channels (64 BCK cycle per stereo frame), crispy audio at 48000Hz breaks down as:

The maths is as follows:

\begin{equation} f_{\text{bck}} = \frac{f_{\text{source}}}{\text{DIVI} + \frac{\text{DIVF}}{4096}} \end{equation}

And so since we are using a 500MHz clock plugging in the above math we get a nice:

\begin{equation} f_{\text{bck}} \approx 3.072 \text{MHz} \end{equation}

Now, remember, each of our frames has 64 BCK cycle per stereo frame, so this gives \(\frac{3.072}{64} = 0.048 \text{Mhz} = 48 \text{kHZ}\) which is sweet.

DWIM for folks like me who have been afflicted with a utter lack of attention span

• CM_PCMCTL: 0x5A000216
• CM_PCMDIV: 0x5A0A2C2B

synth notes

Music is math.

\begin{equation} x\qty(t) = \sin \qty(2\pi ft) \end{equation}

But computers only do discrete math.

\begin{equation} x[n] = \sin \qty(2\pi f \frac{n}{f_{s}}) \end{equation}

where \(f_{s}\) is the same rate and \(n\) is the sample ID.

aliasing

Mathematically speaking, the above is all fine and good but you’ll notice a persnickety thing about mathematics. The nyquest limit, which is half the sample rate, is the maximum rate of the signal that can be represented by sampling without aliasing. What do I mean by aliasing? Consider \(f_{s} = 48000\), \(f=48000\):

\begin{equation} x[n] = \sin \qty(2\pi 48000 \frac{n}{48000}) = \sin \qty(2\pi n) = 0 \end{equation}

and so, no matter what your choice of \(n\) is, the signal will always be zero. This is rather cheeky.